Technical Field
This invention relates generally to the field of semiconductor photolithography and, more particularly, to model-based generation of dummy features for improved target design printability.
Related Art
In conventional photolithographic processing, integrated circuits are created on a semiconductor wafer by exposing the wafer with a pattern of features on a mask or reticle. The pattern of features selectively exposes photosensitive chemicals on a wafer that is then further chemically and mechanically processed to build up layers of the integrated circuit.
As the features on a mask become smaller and smaller, optical distortions can occur whereby the exposure pattern created on a wafer will not match the pattern of features on the mask. To correct this, numerous resolution enhancement techniques (RETs) may be employed to improve the image quality so that the exposure pattern on a wafer more faithfully matches the pattern of features desired. Such RETs often comprise making extensive changes to the corresponding pattern of features on a mask to compensate for the known distortions in the imaging process.
With conventional resolution enhancement techniques, data for a pattern of mask features are analyzed with a computer program to estimate how a corresponding pattern of features will print on a mask. The data for the individual mask features or portions thereof may be adjusted such that the pattern created on the wafer will more faithfully match the desired layout. In addition, features, such as sub-resolution assist features (SRAFs), may be added to the layout data as necessary to improve printing fidelity. Typically, SRAFs are non-printing shapes (e.g., rectangles) that are positioned adjacent to an edge of a feature in order to improve the contrast of the feature, which assists/improves the process during photolithography. The shape, size, and placement of the SRAFs may be predetermined, and often follow simple geometric rules. It is generally desirable to use an aggressive SRAF strategy (e.g., larger SRAF elements) to improve the imaging quality during photolithography, and to improve the pattern transfer immunity against photolithography process variations.
Typically, SRAFs are prevented from printing because, for some levels, a printing SRAF can be a defect that contributes to random defect generation (e.g., when a printing SRAF forms a resist line). Furthermore, multiple stacked printing SRAFs in integrated levels can form an unintended electrical path to signals that can alter or even destroy the circuit behavior.
In one prior art approach, SRAF printing is enabled using a gridded pitch having an optimized RET (illumination/source distribution). This approach incorporates a trim mask, which allows the SRAF to be printed, because the SRAFs are subsequently removed during a trimming phase. Unfortunately, this approach is constrained by the presence of the trim mask, which is not always desired.